Inside a chip package

Nickel-plated copper, with a raised plateau where the heatsink presses down and a foot bonded to the substrate all round. The mark plate and the data matrix in its corner say which part it is and where it was made.

A thin sheet of indium, a soft metal, soldered between the silicon and the lid. A paste would do for a laptop; at several hundred watts the heat needs metal to cross.

Eight stacks of high-bandwidth memory, four along each long side. Each is eight DRAM dies on a base logic die, wired straight down through the silicon, with a wide bus that runs only millimetres to the compute die beside it.

Two dies, each about as large as a lithography scanner can expose in one shot, joined edge to edge by a die-to-die link so software sees one chip. Two banks of cores sit either side of the shared cache, with PHY lanes along the edges that face the memory.

Copper microbumps a few tens of micrometres apart, tens of thousands under each die and stack, sealed in epoxy underfill that flares out in a fillet from every edge.

Passive silicon, larger than one exposure, so it is printed in stitched pieces. Its fine wiring carries the bundles from die to memory and across the die-to-die link; through-silicon vias take power and signals down to the bumps. Chip on wafer on substrate: CoWoS.

Solder bumps a little over a tenth of a millimetre apart, joining the interposer to the substrate.

Organic build-up layers either side of a stiff core, joined through it by plated vias, fanning the connections out to a pitch a board can use. Rows of capacitors round the edge hold the supply steady when the dies suddenly draw more current.

Solder balls about a millimetre apart join the package to the board, with the centre left open for capacitors right under the core power.

Closed, the lid and its foot are all there is to see: one part number, one copper block on a board.

Epoxy cast round the dies and ground flush with the top one, so the bare silicon on top meets the heat spreader. SK hynix lets the same compound flow into the gaps between the dies (MR-MUF); opened, it is left behind as an outline.

The last DRAM die. Nothing sits above it, so it needs no vias, and it is left thick so the whole stack grinds to the height the standard sets (720 µm for HBM3E), level with the compute die beside it.

Seven more memory dies, each thinned to a few tens of micrometres. Each holds banks of cells for its share of the stack's channels, around a band of vias down the middle. They face down; the drawing shows their layout as if through the silicon.

Copper columns a few micrometres wide running straight down through every die, thousands of them, cut open here along one row. A wire bond can only leave from a die's edge, which caps it at a few hundred connections; going through the middle is how the stack reaches a 1024-bit bus (2048 in HBM4).

A copper pillar with a solder cap under every via, a few tens of micrometres apart, and dummy bumps across the arrays that carry no signal, only heat and weight. A thin non-conductive film or the mould fills the gap. Hybrid bonding, copper straight onto copper, will replace the bumps in the tallest stacks.

A logic die, not memory. Its PHY along the edge facing the compute die drives the bus; between them sit the channel controllers, error correction, self-test and the logic that swaps in spare vias. The pads on the far edge are a test port. From HBM4 it is made on a foundry logic process and can carry a customer's own logic.

Larger microbumps join the base die to the interposer: a dense field under the PHY for the data lines, power and ground across the rest, sealed in underfill that flares out at the edge.

The silicon slab the stack and the compute die share. Fine wiring on top runs one wire per data line, a millimetre or two from under the PHY to the pads where the compute die's PHY lands; wide vias take power down to the substrate.

Thousands of narrow trenches etched into the interposer under the stack and lined as capacitors. They hold the supply steady right under the dies, where a phone puts small silicon capacitors under its package instead.

Closed, it is a small block of epoxy with bare silicon on top, a few millimetres from the compute die on the same slab of interposer.

Silicon nitride over silicon oxide seals the die against moisture and the stray ions that would drift into the transistors, and a layer of polyimide over that cushions it against the package. The only holes are over the pads, where the bumps land. Round the die’s edge, every metal level stacked solid makes a seal ring against cracks from the saw.

The one level that is not copper: a micrometre or more of aluminium, which does not corrode in air, takes a probe needle at wafer test, and is what a bump or a wire bond lands on. Vias under it reach the top copper; straps beside it carry the capacitor and the power grid.

Metal, insulator, metal: thin plates of titanium nitride with a high-k film between them, stacked three or four deep with alternate plates joined. Spread under the top metal, they hold charge right on the power grid, so a burst of switching does not drag the supply down.

The top two copper levels, micrometres wide and many times thicker than the levels below. Thick is cheap to run far, so they carry the power grid and the clock across the whole die, and the longest signals.

Levels at two to four times the tightest pitch, carrying signals between blocks: from one unit of a core to the next, or out to the cache, over tens to hundreds of micrometres. Each still turns a right angle from the level below, so any point reaches any other in a few turns.

M0 up to about M3, at the tightest pitch lithography allows, around 23 to 32 nm on today’s leading nodes: they wire transistors into gates and gates into cells. Each level is a trench etched into low-k glass, lined with a barrier a couple of nanometres thick so the copper cannot escape, filled, polished flat, then capped with silicon carbonitride: the thin line over every level. At these widths the barrier is much of the line, so the narrowest use cobalt or ruthenium instead.

Short pillars joining a line to the one crossing beneath it. Each is filled with its line above in one go (dual damascene), so a via and its line are one piece of copper. A chip has billions; the router doubles them where it can, so one bad via does not break a net, and at the tightest pitches their resistance, not the lines’, sets the speed.

The middle of the line, where wiring meets silicon. Trench contacts of tungsten or cobalt run down between the gates onto every source and drain, through a thin silicide that keeps the resistance low, and vias land on them from M0. A dielectric cap on each gate lets a gate contact drop straight onto the gate over the transistor itself without touching the trench contact beside it.

Gate-all-around nanosheets, as in TSMC N2, Samsung SF3 and Intel 18A: three sheets of silicon about 5 nm thick, the gate wrapping all four sides of each, a gate about every 50 nm. The gate is a film of hafnium oxide under work-function metals; the source and drain are crystal grown from the sheets’ ends, phosphorus-doped silicon for n, boron-doped silicon-germanium for p. The right-hand cut goes through one gate as it crosses two n rows and two p rows: an nFET and a pFET sharing one input, the CMOS inverter. In the middle, a dummy gate cuts down into the silicon instead: a break between two cells.

The wafer, about 775 µm thick before it is thinned, and all of it scaffolding except the top few hundred nanometres. Implants make a p-type well under the nFETs and an n-type well under the pFETs; trenches filled with oxide isolate each ridge of active silicon from the next. Intel 18A and TSMC A16 go further and feed power from underneath, through the back of a thinned wafer, so the front metal carries only signals.

Closed, the block is what the bump sees: passivation with one opening over an aluminium pad, and under it every layer the chip has.