// 0x00. introduction_
Idesignsilicon,
notsoftware.
(ai is eating the chip flow.)(ai is eating the chip flow.)
now
Senior Design & AI Engineer — ASIC front-end, verification, SoC architecture & DFT. Now architecting AI Harness, an internal agentic AI platform (LangGraph, RAG, MCP), and brought Claude into production company-wide.
stack
SV, UVM, py, tcl, bash
+MCP / RAG / AI harness
+eda tools
status
open to chat and collaborate
// fsm: routine_sequencer (state=IDLE, hour=8AM, task=0/3)
WORK_BLOCKMEETINGCODEVERIFYDOCSIDLEEATGYMSPORTCODING
~/career — zsh
click to type · try: ls (list files), cat <file> (read one), whoami, sudo hire-me, neofetch, clear (reset)
module juan_kok (); // current_state = SENIOR_AI_ENG
gradpromo??learn(ai)UNI19-23ASIC23-25SENIOR25-now???next
◀
// skill_monitor.sv
[1/5] OVERVIEW
▶
// vitals
22
Skills
847
Commits
3
Years
2
Tape-outs
12
Projects
// output rate — live
~/syslog — monitor
// proficiency
// skill growth — live
1m
5m
15m
▶
smooth
gain70
% proficiency
timeline
// commit streak
// explore — each module links to a dedicated skill page
asic.core ›
ai.pipeline ›
eda.toolchain ›
scripts.src ›
SKILLS: 22 | COMMITS: 847 | TAPE_OUTS: 2 | YEARS_EXP: 3 | ATPG_COV: 90%+ | LANGUAGES: 6 | EDA_TOOLS: 12 | PROJECTS: 12 | OSS_REPOS: 4SKILLS: 22 | COMMITS: 847 | TAPE_OUTS: 2 | YEARS_EXP: 3 | ATPG_COV: 90%+ | LANGUAGES: 6 | EDA_TOOLS: 12 | PROJECTS: 12 | OSS_REPOS: 4
// asic.core
SystemVerilog →RTL Coding →UVM →AMBA AXI/AHB →PCIe / DDR →ECC Safety →
// clk_domain
// parameters
500M
CLK_FREQ
5
PIPE_DEPTH
64K
CACHE_SZ
0.9V
VDD
// bench
ATPG Cov
90%+
Lint
clean
Safety
ASIL-B
SKILLS: 22 | COMMITS: 847 | TAPE_OUTS: 2 | YEARS_EXP: 3 | ATPG_COV: 90%+ | LANGUAGES: 6 | EDA_TOOLS: 12 | PROJECTS: 12 | OSS_REPOS: 4SKILLS: 22 | COMMITS: 847 | TAPE_OUTS: 2 | YEARS_EXP: 3 | ATPG_COV: 90%+ | LANGUAGES: 6 | EDA_TOOLS: 12 | PROJECTS: 12 | OSS_REPOS: 4
// ai.pipeline
LLM Tooling →MCP Servers →RAG Pipelines →AI Agents →Vibe Coding →
// skill growth — live
% growth
timeline
// output rate — live
output
timeline
// parameters
0.7
TEMP
40
TOP_K
32k
CTX_LEN
16
BATCH
// bench
Test Cov
90%+
Tests
322
Context
32k
SKILLS: 22 | COMMITS: 847 | TAPE_OUTS: 2 | YEARS_EXP: 3 | ATPG_COV: 90%+ | LANGUAGES: 6 | EDA_TOOLS: 12 | PROJECTS: 12 | OSS_REPOS: 4SKILLS: 22 | COMMITS: 847 | TAPE_OUTS: 2 | YEARS_EXP: 3 | ATPG_COV: 90%+ | LANGUAGES: 6 | EDA_TOOLS: 12 | PROJECTS: 12 | OSS_REPOS: 4
// eda.toolchain
TestMax
DC
RTL-Arch
Spyglass
Verdi
Verilator
// bench
Lint Pass
95%
Synth QoR
88%
Sim Speed
76%
// scripts.src
// commit log
lines
week
// 0x11. selected_work_

selected work

live from github.com/JuanSync7
// system.low_power_mode
off the clock · abs. max ratings
ultimate frisbee
badminton
swimming
piano
travelling
vibe coding
ultimate frisbee
badminton
swimming
piano
travelling
vibe coding
ultimate frisbee
badminton
swimming
piano
travelling
vibe coding