featured
Inference, end to end
A visual walkthrough of LLM inference from prompt to token — prefill vs decode, the KV-cache, precision, speculative decoding, the memory hierarchy, and how the big labs serve at scale.
How Inference Chips Are Built
From transistors and dataflow to wafer-scale engines — a visual tour of how the silicon behind AI inference is designed, and why startups think they can unseat the GPU.
RTL to GDS: A Complete Walkthrough
From Verilog to tapeout — the full ASIC design flow broken down into digestible steps. Covering synthesis, P&R, timing closure, and the dark arts of DRC.
Building a Cyberpunk Portfolio with Astro
How I turned terminal aesthetics and chip schematics into a personal site. Starfields, FSM diagrams, and unhealthy amounts of CSS.
research.feeds
scheduled deep-research jobs. each feed runs on its own cadence and appends a new edition — a post + dashboard — every cycle.
inference engines
weekly tracker of the LLM inference-engine landscape — vLLM, SGLang, TensorRT-LLM, LMDeploy, llama.cpp and friends. open the live dashboard →
frontier models
weekly tracker of the AI model landscape — frontier closed/open, small & on-device, agentic frameworks, classifiers. open the live dashboard →
inference silicon
weekly tracker of the chips powering inference — NVIDIA/AMD GPUs, wafer-scale, dataflow LPUs, inference ASICs, RISC-V. open the live dashboard →
entries
Inference, end to end
A visual walkthrough of LLM inference from prompt to token — prefill vs decode, the KV-cache, precision, speculative decoding, the memory hierarchy, and how the big labs serve at scale.
How Inference Chips Are Built
From transistors and dataflow to wafer-scale engines — a visual tour of how the silicon behind AI inference is designed, and why startups think they can unseat the GPU.
RTL to GDS: A Complete Walkthrough
From Verilog to tapeout — the full ASIC design flow broken down into digestible steps. Covering synthesis, P&R, timing closure, and the dark arts of DRC.
Building a Cyberpunk Portfolio with Astro
How I turned terminal aesthetics and chip schematics into a personal site. Starfields, FSM diagrams, and unhealthy amounts of CSS.
Neural Networks on FPGAs: A Practical Guide
Deploying quantized models on Xilinx Zynq. Covers HLS, resource budgeting, and why your first attempt will always be too slow.
My Vim Setup for ASIC Design
bulletin
FPGA neural net vs. GPU
Head-to-head latency and throughput on quantized inference.
Migrate EDA scripts to Python 3.12
Exorcising the last Python 2 ghosts from the synthesis flow.
Coffee shop tier list update
Re-ranking the local espresso spots. Methodology disputed.
Timing closure on 7nm block
Chasing the last 40ps of setup slack across three clock domains.
RISC-V branch predictor series
A multi-part deep dive on speculative fetch and recovery.
Starfield performance on mobile
Profiling the canvas starfield to hold a steady 60fps on phones.
vim + SystemVerilog LSP tutorial
Completion, lint and go-to-def for RTL right inside vim.
RTL-to-GDS series, part 2
From gate-level netlist all the way to final tapeout.
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